IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 251

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Complex Type Library
Complex AddSub
Table 3–6. Complex AddSub Block I/O Formats
Figure 3–2. Complex AddSub Block Example
© June 2010 Altera Corporation
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
...
In
I(n+1)
I(n+2)
O1
1)Imag(max(L1,Ln)
+ 1),(max(RI,Rn) + 1)
[L].[R]
Real([L1].[R1])Imag([L1].[R1])
Real([Ln].[Rn])Imag([Ln].[Rn])
Real(max(L1,Ln) + 1),(max(RI,Rn) +
Table
is an input port. O1
Simulink (2),
[1]
[1]
3–6:
Table 3–6
Figure 3–2
(3)
[L].[R]
is an output port.
shows the Complex AddSub block I/O formats.
I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
...
InReal: in STD_LOGIC_VECTOR({LPn + RPn - 1} DOWNTO 0)
InImag: in STD_LOGIC_VECTOR({LPn + RPn - 1} DOWNTO 0)
I(n+1): in STD_LOGIC
I(n+2): in STD_LOGIC
O1Real: out STD_LOGIC_VECTOR({max(LI,Ln) + max(RI,Rn)} DOWNTO 0)
O1Imag: out STD_LOGIC_VECTOR({max(LI,Ln) + max(RI,Rn)} DOWNTO 0)
shows an example with the Complex AddSub block.
(Note 1)
Preliminary
VHDL
DSP Builder Standard Blockset Libraries
Implicit
Implicit
Implicit
Implicit
Implicit
Implicit
Type
(4)
3–5