IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 62

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–18
Reference Timing Diagram
Figure 3–17. Single-Clock Timing Relationships
Figure 3–18. Multiple-Clock Timing Relationships
DSP Builder Standard Blockset User Guide
Figure 3–17
fed by the output of a counter. The counter output begins at 10—the value is 10 during
the first Simulink clock step.
This timing is not true when crossing clock domains. For example,
the timing delays in a design with a derived clock that has half the base clock period.
In general, DSP Builder is not cycle-accurate when crossing clock domains.
shows the timing relationships in a hypothetical case where a register is
Preliminary
Timing Semantics Between Simulink and HDL Simulation
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
Figure 3–18
shows