IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 416

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Index–2
Comments
Comparator block
Complex AddSub block
Complex Conjugate block
Complex Constant block
Complex Delay block
Complex Multiplexer block
Complex Product block
Complex to Real-Imag block
Complex Type library
Constant block
Controlling synthesis and compilation
Counter block
Custom library
Cyclone II DE2 DSP board
Cyclone II EP2C35 DSP board
Cyclone II EP2C70 DSP board
Cyclone III EP3C120 DSP board
Cyclone III EP3C25 DSP board
D
Data width propagation
Decoder block
Delay block
Demultiplexer block
Design flow
Design rules
Device family support
Differentiator block
Digital signal processing (DSP)
Display Pipeline Depth block
Divider block
Down Sampling block
DSP block
DSP development board
DSP Builder Handbook Volume 2: DSP Builder Standard Blockset
Using advanced PLL features
Using Clock and Clock_Derived blocks
Adding to a block
Adding to the library browser
Creating a library model file
Walkthrough
Control using Signal Compiler
Overview
Using a State Machine Editor block
Using a State Machine Table Block
Using Hardware in the loop
Using MegaCore functions
Bit width
Frequency
Signal Compiler
Standard blockset
Board description file
Component description file
Creating a board library
2–10
9–2
2–1
3–1
3–4
2–9
2–1
2–6
4–7
3–8
6–10
9–1
2–5
2–8
3–19
4–8
3–9
3–22
3–1
1–1
9–3
3–11
3–4
3–4
3–8
10–4
3–6
11–2
3–10
10–6
3–13
1–4
11–3
11–4
11–6
4–2
1–3
10–2
11–6
5–1
9–1
3–15
9–5
3–19
3–19
11–2
11–7
3–10
Preliminary
Dual-Clock FIFO block
Dual-Port RAM block
E
Error message
Example designs
Creating a new board description
predefined components
Supported boards
Troubleshooting
Data type mismatch
Design includes pre-v7.1 blocks
Loop while propagating bit widths
Output connected to Altera block
Unexpected end of file
When generating blocks
32 tap FIR filter
Amplitude modulation
Avalon-MM Blocks
Avalon-MM FIFO
CIC decimation
CIC interpolation
Color space converter
Combined blocksets
Convolution interleaver deinterleaver
CORDIC, 20 bits rotation mode
Custom Library
Custom library block
Cyclone II DE2 board
Cyclone II EP2C35 board
Cyclone II EP2C70 board
Cyclone III EP3C120 board (7-seg display)
Cyclone III EP3C120 board (HSMC A)
Cyclone III EP3C120 board (HSMC B)
Cyclone III EP3C120 board (LED/PB)
Cyclone III EP3C25 starter board
Farrow based resampler
Getting started tutorial
Hardware in the loop
HDL Import
HDL import
HIL frequency sweep
IIR filter
Imaging edge detection
MAC based 32 tap FIR filter
Quartus II assignment setting
SignalTap II
SignalTap II filtering lab
SignalTap II filtering lab with loopback
SOPC Builder peripheral
State machine example
State Machine Table
Stratix EP1S25 board
13–10
13–6
6–2
8–1
13–5
13–6
13–6
13–5
13–5
13–6
9–7
10–1
13–4
9–4
13–4
13–6
13–5
13–12
13–10
9–1
13–9
5–3
13–3
13–7
© June 2010 Altera Corporation
13–10
2–4
11–1
13–3
13–8
10–1
13–7
13–7
13–8
7–8
13–9
13–9
13–7
13–8
13–8
13–6
13–9
13–5
10–1
13–4
13–9
13–10
13–6
13–10
13–9