IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 404

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

13–8
CORDIC, 20 bits Rotation Mode
Imaging Edge Detection
Quartus II Assignment Setting Example
SignalTap II Filtering Lab
DSP Builder Standard Blockset Libraries
f
f
This design example illustrates a Farrow resampler. You can simulate its performance
in MATLAB, change it as required for your application, generate VHDL and
synthesize the model to Altera devices. The design example has an input clock rate
identical to the system clock. For applications where the input rate is much lower than
the system clock, time sharing should be implemented to achieve a cost effective
solution.
The example model is FarrowResamp.mdl.
For more information about this design, click on the Doc symbol in the design model
window.
This design example illustrates an iterative 20 bit rotation mode, which computes sine
and cosine angles and implements with the coordinate rotation digital computer
(CORDIC) algorithm.
The example model is DemoCordic.mdl.
This design example illustrates an edge detection design.
The example model is Edge_detector.mdl.
Refer to
detector design.
This design example illustrates Quartus II assignment setting from DSP Builder. You
can launch the
Stratix EP2S60 DSP development board.
The example model is Top_2s60Board.mdl.
Two numerically-controlled oscillators generate a 833.33kHz sinusoidal signal and a
83.33kHz sinusoidal signal. The design example adds the signals together. The
resulting signal loops back to a low-pass 34-tap filter with 14-bit fixed-point
coefficients. The low-pass filter removes the 833.33-kHz sinusoidal signal and allows
the 83.33-kHz sinusoidal signal through to the fir_result output.
The example model is FilteringLab.mdl.
AN364: Edge Detection Reference Design
Signal Compiler
Preliminary
block to compile the design and program the
for a full description of the edge
© June 2010 Altera Corporation
CORDIC, 20 bits Rotation Mode
Chapter 13: Design Examples