IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 283

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Gate & Control Library
Multiplexer
Table 4–35. Multiplexer Block Parameters
Table 4–36. Multiplexer Block I/O Formats
© June 2010 Altera Corporation
Number of Input Data Lines An integer greater than
Number of Pipeline Stages
One Hot Select Bus
Use Enable Port
Use Asynchronous Clear
Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
input)
I2
….
Ii
…
In[
In+1
In+2
O1
with (0 < I < i + 1)
[L].[R]
[Li].[Ri]
[LS].[0]
[L2].[R2]
Simulink (2),
Ln].[Rn]
[max(Li)].[max(Ri)]
Table
[1
[1
is an input port. O1
Name
]
]
(select
4–36:
(3)
Table 4–34. Multiplexer Block Inputs and Outputs
Table 4–35
Table 4–36
Figure 4–14
sel
0–(n-1)
ena
aclr
<unnamed>
[L].[R]
I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L2 + R2 - 1} DOWNTO 0)
…
Ii: in STD_LOGIC_VECTOR({Li + Ri - 1} DOWNTO 0)
….
In: in STD_LOGIC_VECTOR({Ln + Rn - 1} DOWNTO 0)
In+1: STD_LOGIC
In+2: STD_LOGIC
O1: out STD_LOGIC_VECTOR({max(Li)) + max(Ri) - 1} DOWNTO 0)
Signal
1 (Parameterizable)
>= 0 (Parameterizable) Specify the number of pipeline stages.
On or Off
On or Off
On or Off
is an output port.
shows the Multiplexer block parameters.
shows the Multiplexer block I/O formats.
shows an example with the Multiplexer block.
Value
Input
Input
Input
Input
Output
(Note 1)
Direction
Specify how many inputs the multiplexer has.
Turn on to use one-hot selection for the bus select signal instead of
full binary.
Turn on to use the clock enable input (ena). This option is available
only when the number of pipeline stages is greater than 0.
Turn on to use the asynchronous clear input (aclr). This option is
available only when the number of pipeline stages is greater than 0.
Preliminary
Select control port.
Data input ports.
Optional enable port.
Optional asynchronous clear port.
Output port.
VHDL
Description
Description
DSP Builder Standard Blockset Libraries
Type
Implicit
Implicit
4–21
(4)