IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 315

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: IO & Bus Library
Bus Concatenation
Bus Concatenation
Table 6–8. Bus Concatenation Block Parameters
Table 6–9. Bus Concatenation Block I/O Formats
Figure 6–6. Bus Concatenation Block Example
© June 2010 Altera Corporation
Output Is Signed
Width of Input a
Width of Input b
I
O
Notes to
(1) For signed integers, the MSB is the sign bit.
(2) [N] is the number of bits.
(3) I1
(4) Explicit means that the port bit width information is a block parameter.
I/O
I1
I2
O1
[N]
[N1]
[N2]
Name
[N1 + N2]
Table
is an input port. O1
Simulink (2),
6–9:
The Bus Concatenation block concatenates two buses.
The block has two inputs, a and b. These may be signed integer or unsigned integer.
The output width is width(a) + width(b).
Input a becomes the MSB part of the output, input b becomes the LSB part.
Table 6–8
Table 6–9
Figure 6–6
(3)
On or Off
>= 1
(Parameterizable)
>= 1
(Parameterizable)
[N]
is an output port.
Value
I1: in STD_LOGIC_VECTOR({N1 - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({N2 - 1} DOWNTO 0)
O1: out STD_LOGIC_VECTOR({N1 + N2 - 1} DOWNTO 0)
shows the Bus Concatenation block parameters.
shows the Bus Concatenation block I/O formats.
shows an example with the Bus Concatenation block.
Turn on if the output bus is signed.
Specifies the width of the first bus to concatenate.
Specifies the width of the second bus to concatenate.
(Note 1)
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Type
Explicit
Explicit
(4)
6–7