IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 199

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 1: AltLab Library
HIL (Hardware in the Loop)
HIL (Hardware in the Loop)
Table 1–12. HIL Block Parameters, Page 1 (Part 1 of 2)
© June 2010 Altera Corporation
Select the Quartus II
project
Select the clock pin
Select the reset pin
Identify the signed
ports
Export
Select the reset level
Burst Mode
Burst Length
Frame Mode
Input Sync
Output Sync
Sampling Period
Name
1
The HIL (Hardware in the Loop) block allows you to use an FPGA as a simulation
device inside a Simulink design. This configuration accelerates the simulation time,
and also allows access to real hardware in a simulation.
To use an HIL block, you need an FPGA development board with a JTAG interface.
Use any JTAG download cable, such as a ByteBlasterMV™, ByteBlaster™, or
USB-Blaster™ cable.
HIL supports advanced features, including:
■
■
This block supports only single clock designs with registered paths in a design. The
simulation results may be unreliable for combinational paths.
Table 1–12
.qpf file
Port name
Port name
Signed or
Unsigned
On or Off
Active_High,
Active_Low
On or Off
On or Off
Port name
Port name
Integer
(Note 1)
Exported ports (allows the use of hardware components connected to the FPGA)
Burst and frame modes (improves HIL simulation speed)
Value
shows the parameters specified in page 1 of the HIL dialog box.
Browse for a Quartus II project file ,which describes the hardware design that the
HIL block uses.
The clock pin name for the hardware design in the Quartus II software.
The reset pin name for the hardware design in the Quartus II software.
Set the number of bits and select the type (signed or unsigned) of each input and
output port in the hardware design.
When on, the selected port is exported on an FPGA pin (or on multiple pins for
buses). When off (the default), the port is exported to the Simulink model.
The reset level that matches the setting in the original design. For designs originated
from the standard blockset, the reset level is specified in the Clock or
Clock_Derived block. If your design uses no clock block, it uses a default clock
with reset level active high. For designs originated from the advanced blockset, the
reset level is specified in the Signals block.
When on, allows sending data to the FPGA in bursts, which improves the simulation
speed, but delays the outputs by the burst length. When Off, it defaults to
single-step mode.
Specify the length of a burst ("1" is equivalent to disabling burst mode). Use higher
values to produce faster simulations (although the extra gain becomes negligible
with bigger burst sizes).
Use in burst mode when data is sent or received in frames. When on, allows
synchronizing of the output data frames to the input data frames.
The input port for the synchronization signal in frame mode.
The output port for the synchronization signal in frame mode.
Specify the sample time period in seconds. (A value of -1 means that the sampling
period is inherited from the block connected to the inputs.)
Preliminary
Description
DSP Builder Standard Blockset Libraries
1–9