IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 235

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Arithmetic Library
Parallel Adder Subtractor
Table 2–40. Multiply Add Block I/O Formats
Figure 2–16. Multiply Add Block Example
Parallel Adder Subtractor
© June 2010 Altera Corporation
I/O
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
….
Ii
…
In[
I(n+1)
I(n+2)
where 3 < n < 9
O1
[R1]
[L].[R]
[L1].[R1]
[L1].[R1]
L1].[R1]
2 x [L1]
Table
Simulink (2),
is an input port. O1
[1]
[1]
+ ceil(log2(n))
2–40:
Figure 2–16
The Parallel Adder Subtractor block takes any input data type. If the input
widths are not the same,
match the largest input width. The generated VHDL has an optimized, balanced
adder tree.
Table 2–41
(3)
[L].[R]
.2 x
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
…
Ii: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
….
In: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I(n+1): in STD_LOGIC
I(n+2): in STD_LOGIC
where 3 < n < 9
O1: out STD_LOGIC_VECTOR({(2 x L1) + ceil(log2(n)) + (2 x R1) - 1} DOWNTO 0) Implicit
shows the Parallel Adder Subtractor block inputs and outputs.
shows an example with the Multiply Add block.
(Note 1)
Signal Compiler
Preliminary
VHDL
sign extends the buses so that they
DSP Builder Standard Blockset Libraries
Explicit
...
Explicit
...
Explicit
Type
(4)
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