IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 399

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 13: Design Examples
Amplitude Modulation
Figure 13–2. Hardware in the Loop Example Model
Amplitude Modulation
HIL Frequency Sweep
© June 2010 Altera Corporation
f
f
f
1
You can display the model corresponding to each design example by clicking Run
this demo in the Help window. For example, if you click Run this demo for the HIL
example, the model design window opens displaying the HIL frequency sweep
model
The <DSP Builder install path>\DesignExamples\Tutorials\ directory contains the
getting started tutorials and design examples.
For more information, refer to the
volume 2 of the DSP Builder Handbook.
You can also access simple example models for most of the blocks in the DSP Builder
blockset that correspond to the examples in the block descriptions. Many of these
example blocks include Simulink Scope blocks that display the output waveforms
when you simulate the models. Access these examples in the directory <DSP Builder
install path>\DesignExamples\Tutorials\UnitBlocks
The Getting Started Tutorial uses the amplitude modulation design example to
demonstrate the DSP Builder design flow. The design example is a modulator that has
a sine wave generator, a quadrature multiplier, and a delay element.
The example model is singen.mdl.
For more information about this design, refer to the Getting Started Tutorial chapter in
the
Handbook.
This HIL design shows a low-pass filter on the output of a modulated sine wave
generation that the CORDIC algorithm creates.
The example model is FreqSweep_HIL.mdl.
For more information about this design, refer to the HIL Example Designs in the Using
Hardware in the Loop (HIL) chapter in the
section in volume 2 of the DSP Builder Handbook.
DSP Builder Standard Blockset User Guide
(Figure
13–2).
Preliminary
DSP Builder Standard Blockset User Guide
DSP Builder Standard Blockset User Guide
section in volume 2 of the DSP Builder
DSP Builder Standard Blockset Libraries
section in
13–3