IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 225

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Arithmetic Library
Increment Decrement
Table 2–24. Gain Block I/O Formats (Part 2 of 2)
Figure 2–9. Gain Block Example
Increment Decrement
Table 2–26. Increment Decrement Block Parameters (Part 1 of 2)
© June 2010 Altera Corporation
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
(5) K is the gain constant with the format K
Bus Type
<number of bits>.[] >= 0
[].<number of bits> >= 0
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
[L].[R]
Name
[L1 + LK].2*max(R1,RK)]
Table
Simulink (2),
is an input port. O1
2–24:
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
(3)
Figure 2–9
The Increment Decrement block increments or decrements a value in time. The
output is a signed integer, unsigned integer, or signed binary fractional number. For
all number formats, the counting sequence increases or decreases by the smallest
representable value; for integer types, the value always changes by 1.
Table 2–25
Table 2–25. Increment Decrement Block Inputs and Outputs
Table 2–26
(5)
ena
sclr
c
[L].[R]
Value
Signal
O1: out STD_LOGIC_VECTOR({L1+LK+2*max(R1,RK)-1} DOWNTO 0)
is an output port.
shows an example with the Gain block.
shows the Increment Decrement block inputs and outputs.
shows the Increment Decrement block parameters.
[LK].[RK]
The number format you want to use for the bus.
Select the number of bits to the left of the binary point, including the sign bit.
Select the number of bits to the right of the binary point. This option applies only
to signed fractional formats.
Input
Input
Output
Direction
(Note 1)
Preliminary
Optional clock enable.
Optional synchronous clear.
Result.
VHDL
Description
Description
DSP Builder Standard Blockset Libraries
Implicit
Type
2–17