IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 373

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 10: State Machine Functions Library
State Machine Table
Design Rule Checks
© June 2010 Altera Corporation
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A conditional statement consists of a current state, a condition that causes a transition
to take place, and the next state to which the state machine transitions. The current
state and next state values must be state names defined in the States tab, which you
can select from drop down list in the dialog box.
To indicate in a conditional statement that a state machine always transitions from the
current state to the next state, specify the conditional expression to be one.
Figure 10–5
default inputs and states.
Figure 10–5. Simple State Transition Table
When VHDL generates, the expression strings for the port names are replaced by
signals named <port name>_sig.
Specify at least one transition for each state. Otherwise, the block does not generate
legal VHDL.
You may experience problems when using very large input signals (greater than 2
The Analyze button in the Design Rule Checks tab of the State Machine Builder
dialog box performs the following checks:
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■
■
■
At least two states must be defined
At least two conditional statements must be defined
All input port names must be unique
All state names must be unique
shows the dialog box that specifies a simple state transition table with the
Preliminary
DSP Builder Standard Blockset Libraries
25
10–5
).