IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 367

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
True Dual-Port RAM
Table 9–38. True Dual-Port RAM Block I/O Formats
Figure 9–13. True Dual-Port RAM Block Example
© June 2010 Altera Corporation
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
I5
I6
I7
I8
O1
[L].[R]
[L1].[R1]
[L2].[0]
[L2].[0]
[L1].[R1]
[L2].[0]
[L2].[0]
[1]
[1]
[L1].[R1]
Table
Simulink (2),
is an input port. O1
9–12:
Table 9–38
Figure 9–13
(3)
[L].[R]
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0)
I3: in STD_LOGIC_VECTOR({L3 - 1} DOWNTO 0)
I4: in STD_LOGIC_VECTOR({L4 + R4 - 1} DOWNTO 0)
I5: in STD_LOGIC_VECTOR({L5 - 1} DOWNTO 0)
I6: in STD_LOGIC_VECTOR({L6 - 1} DOWNTO 0)
I7: in STD_LOGIC
I8: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
shows the True Dual-Port RAM block I/O formats.
shows an example with the True Dual-Port RAM block.
(Note 1)
Preliminary
VHDL
DSP Builder Standard Blockset Libraries
Type
Explicit
Explicit
9–27
(4)