IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 272

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–10
Flipflop
Table 4–17. Flipflop Block Parameters
DSP Builder Standard Blockset Libraries
Mode
Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Name
1
DFFE or TFFE
Signed Integer,
Signed Fractional,
Unsigned Integer,
Single Bit
(Parameterizable)
(Parameterizable)
Set the Flipflop block as a D-type flipflop with enable (DFFE) or T-type flipflop
with enable (TFFE).
If the number of bits is set to more than 1, the block behaves as single-bit flipflops for
each bit. For example, for a TFFE flipflop with an n-bit signal, the signal is processed
with n 1-bit TFFE flipflops.
Table 4–16
Table 4–16. Flipflop Block Inputs and Outputs
DFFE mode:
TFFE mode:
DSP Builder does not support (aclrn == 0) and (aprn == 0).
The aclrn port is an active-low asynchronous clear port. When active this sets the
output and internal state to 0 for the remainder/duration of the clock cycle.
The aprn port is an active-low asynchronous preset port. When active this sets the
output and internal state to 1 for the remainder/duration of the clock cycle.
Table 4–17
input
ena
aprn
aclrn
Q
if (0 == aclrn)
else if (0 == aprn)
else if (1 == ena)
if (0 == aclrn)
else if (0 == aprn)
else if (1 == ena) and (1 == T)
Value
Signal
shows the Flipflop block inputs and outputs.
shows the Flipflop block parameters.
Input
Input
Input
Input
Output
Specify the type of flipflop to implement.
Specify the bus number format that you want to use.
Specify the number of bits to the left of the binary point.
Specify the number of bits to the right of the binary point for the gain. This
option is zero (0) unless you select Signed Fractional.
Direction
Q = 0;
Q = 0;
Preliminary
Q = D
Data or togggle port.
Enable port.
Asynchronous reset port.
Asynchronous clear port.
Output port.
Q = 1;
Q = 1;
Q = toggle
Description
Description
Chapter 4: Gate & Control Library
© June 2010 Altera Corporation
Flipflop