IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 384

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

11–10
Figure 11–9. Configured PLL in the Quartus II Block Design Editor
DSP Builder Standard Blockset Libraries
1
4. Open a Quartus II project and configure a PLL to produce the required output
Each output clock is negated in the block editor to produce a the signals pclk0p,
pclk0n, pclk1p, and pclk1n.
5. Import the PLL into the test design model:
Figure 11–10. PLL Subsystem
clocks:
a. Create a new block design file (for example, pll_clkout.bdf) and use the
b. Configure the PLL with a 50MHz input clock (inclk0) and no other optional
c. Click Create HDL File for Current File on the File menu.
a. Add a
b. Open the subsystem (pll_clkout) and remove the default input port. Specify
c. Assign appropriate pin assignments for the four output clocks on the test
MegaWizard™ Plug-in Manager to add an ALTPLL megafunction.
inputs. (Turn off areset.) Turn on Create ‘locked’ output. Add two additional
output clocks with 180 and 270 degrees phase shift from the input clock (c1
and c2) and clock multiplication factor of 2.
Figure 11–9
and browse for the HDL file created in step
subsystem.
the clock name (such as clkin_50) in the block parameters for the HDL
Entity block. This name should match the clock name in the .bdf file.
design model
Subsystem Builder
shows the completed block design file.
(Figure
Preliminary
11–10.)
block to your model. Double-click on the block
4c
then click Build to create the
© June 2010 Altera Corporation
Cyclone III EP3C120 DSP Board
Chapter 11: Boards Library