IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 322

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–14
Figure 6–11. GND Block Example
Input
Table 6–22. Input Block Parameters
DSP Builder Standard Blockset Libraries
Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Specify Clock
Clock
Name
Signed Integer,
Signed Fractional,
Unsigned Integer,
Single Bit
(Parameterizable)
(Parameterizable)
On or Off
User defined
(Parameterizable)
The Input block defines the input boundary of a hardware system and casts
floating-point Simulink signals (from generic Simulink blocks) to signed binary
fractional format (feeding DSP Builder blocks).
Table 6–22
Table 6–23 on page 6–15
Value
shows the Input block parameters.
Specifies the number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign bit.
This parameter does not apply to single-bit buses.
Specifies the number of bits to the right of the binary point. This parameter
applies only to signed fractional buses.
Turn on to explicitly specify the clock name.
Specifies the name of the required clock signal.
shows the Input block I/O formats.
Preliminary
Description
© June 2010 Altera Corporation
Chapter 6: IO & Bus Library
Input