IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 317

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: IO & Bus Library
Bus Splitter
Figure 6–7. Bus Conversion Block Example
Bus Splitter
Table 6–12. Bus Splitter Block Parameters
Table 6–13. Bus Splitter Block I/O Formats (Part 1 of 2)
© June 2010 Altera Corporation
Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
I
I/O
I1
where n is the number of inputs
Name
[LP].[RP]
Simulink (2),
with LP + RP = n
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
Figure 6–7
The Bus Splitter block splits a bus into single-bit outputs.
The output ports are numbered from LSB to MSB. You can specify the bus type that
you want to use, and specify the number of bits on either side of the binary point.
Table 6–12
Table 6–13
(3)
Value
shows a design example with the Bus Conversion block.
shows the Bus Splitter block parameters.
shows the Bus Splitter block I/O formats.
I1: in STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign bit.
Specifies the number of bits to the right of the binary point. This parameter
applies only to signed binary fractional buses.
Preliminary
(Note 1)
VHDL
Description
DSP Builder Standard Blockset Libraries
Type
Explicit
(4)
6–9