IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 233

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Arithmetic Library
Multiply Add
Table 2–37. Multiply Accumulate Block I/O Formats
Figure 2–15. Multiply Accumulate Block Example
Multiply Add
© June 2010 Altera Corporation
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2[
I3
I4
I5
I6
O1[
[L].[R]
[L1].[R1]
[1]
[1]
[1]
[1]
L2].[R2]
Table
Simulink (2),
LO].[RO]
is an input port. O1
2–37:
(3)
The sload input controls the accumulator feedback path. If the accumulator is
adding and sload is high, the multiplier output is loaded into the accumulator. If the
accumulator is subtracting, the opposite (negative value) of the multiplier output is
loaded into the accumulator.
Figure 2–15
The Multiply Add block consists of two, three, or four multiplier pairs feeding a
parallel adder. The operands in each pair are multiplied together and the second and
fourth multiplier outputs can optionally be added to or subtracted from the total.
The following equation expresses the block function:
The operand b inputs can optionally be hidden and instead have constant values
assigned in the Block Parameters dialog box.
The input is a signed integer, unsigned integer, or signed binary fractional formats.
Table 2–38
[L].[R]
y = a0×b0 ± a1×b1 [+ a2×b2 [± a3×b3]]]
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L2 + R2 - 1} DOWNTO 0)
I3: in STD_LOGIC
I4: in STD_LOGIC
I5: in STD_LOGIC
I6: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L0 + R0 - 1} DOWNTO 0)
is an output port.
shows the Multiply Add block inputs and outputs.
shows an example with the Multiply Accumulate block.
(Note 1)
Preliminary
VHDL
DSP Builder Standard Blockset Libraries
Explicit
Explicit
Explicit
Type
(4)
2–25