IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 94

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–6
Figure 5–5. Scope Output from the FrequencySweep Model with HIL Block
Burst and Frame Modes
DSP Builder Standard Blockset User Guide
17. Simulate your design in Simulink.
The Quartus II software infrastructure that communicates with the FPGA through
JTAG—system-level debugging (SLD)—uses a serial data transfer protocol.
To maximize the throughput of this data transfer, the HIL block offers a burst mode
that buffers the stimulus data and presents it in bursts to the hardware. Burst mode
also allows a frame mode for certain types of designs.
Table 5–1
with the normal single-step mode.
Table 5–1. Comparing Single-Step and Burst Modes
Single step
Burst
finished design.
Mode
shows the advantages and disadvantages of using burst mode compared
Cycle accurate simulation.
Feedback is possible outside of
the HIL block.
■
■
■
Low SLD overhead.
Fast HIL results.
Frame mode possible.
Advantages
Preliminary
Figure 5–5
■
■
A latency is introduced on the output signals of
the HIL block making feedback loop difficult
outside the FPGA device.
High SLD overhead.
No frame mode.
shows the scope display from the
Disadvantages
© June 2010 Altera Corporation
Burst and Frame Modes
Chapter 5: Using HIL