IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 282

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–20
Table 4–32. Logical Reduce Operator Block Parameters (Part 2 of 2)
Table 4–33. Logical Reduce Operator Block I/O Formats
Figure 4–13. Logical Reduce Operator Block Example
Multiplexer
DSP Builder Standard Blockset Libraries
[].[number of bits] >= 0
Logical Reduction
Operation
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
[L].[R]
Name
[L1].[R1]
[1]
Table
Simulink (2),
is an input port. O1
4–30:
(Parameterizable)
AND, OR, XOR,
NAND, NOR
Table 4–33
Figure 4–13
The Multiplexer block operates as either a n-to-1 one-hot or full-binary bus
multiplexer with one select control. The output width of the multiplexer is equal to
the maximum width of the input data lines. The block works on any data type and
sign extends the inputs if there is a bit width mismatch.
Table 4–34
(3)
[L].[R]
Value
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: out STD_LOGIC
shows the Logical Reduce Operator block I/O formats.
shows the Multiplexer block inputs and outputs.
shows an example with the Logical Reduce Operator block.
Specify the number of bits to the right of the binary point.
Specify the logical operation to perform.
Preliminary
(Note 1)
VHDL
Description
Chapter 4: Gate & Control Library
© June 2010 Altera Corporation
Multiplexer
Type
Explicit
Explicit
(4)