IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 352

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–12
Table 9–16. LUT Block Parameters
Table 9–17. LUT Block I/O Formats
DSP Builder Standard Blockset Libraries
Address Width
Data Type
[number of bits].[]
[].[number of bits]
MATLAB Array
Use Enable Port
Register Data
Use LPM
Register Address
Memory Block Type AUTO, M512, M4K,
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
O1
[L].[R]
Name
[L1].[0]
[1]
[LPO].[RPO]
Table
Simulink (2),
is an input port. O1
9–17:
2–16
Signed Integer,
Signed Fractional,
Unsigned Integer,
Single Bit
>= 0
(Parameterizable)
>= 0
(Parameterizable)
User Defined
(Parameterizable)
On or Off
On or Off
On or Off
On of Off
M9K, MLAB, M144K
Table 9–16
Table 9–17
(3)
[L].[R]
Value
is an output port.
I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
I2: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({LPO + LPO - 1} DOWNTO 0)
shows the LUT block parameters.
shows the LUT block I/O formats.
(Note 1)
The data type format that you want to use.
Specify the number of data bits stored on the left side of the binary point
including the sign bit.
Specify the number of data bits stored on the right side of the binary point.
This field must be a one-dimensional MATLAB array with a length smaller than
2 to the power of the address width. A warning is given if the values in the
MATLAB array cannot be exactly represented in the chosen data format.
Turn on to use the optional clock enable input (ena).
Turn on to register the output result.
When on, the look-up table implements as case conditions with the lpm_rom
library of parameterized modules (LPM) function. You should turn on this
option for large look-up tables, for example, greater than 8 bits. The input
address always registers when this option is on.
When register address is on, the input address bus generates. If you use LPM,
the input address is always registered.
The RAM block type. Some memory types are not available for all device types.
The address width as an unsigned integer.
Preliminary
VHDL
Description
© June 2010 Altera Corporation
Chapter 9: Storage Library
LUT (Look-Up Table)
Type
Explicit
(4)