MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 121

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PTD[1:0] — Port D Data Bits
TACH[1:0] — Timer Channel I/O Bits
12.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a 1 to a
DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.
DDRD[1:0] — Data Direction Register D Bits
Freescale Semiconductor
PTD[1:0] are read/write, software programmable bits. Data direction of each port D pin is under the
control of the corresponding bit in data direction register D.
The PTD1/TACH1–PTD0/TACH0 pins are the TIMA input capture/output compare pins. The
edge/level select bits, ELSxB–ELSxA, determine whether the PTD1/TACH1–PTD0/TACH0 pins are
timer channel I/O pins or general-purpose I/O pins. See
These read/write bits control port D data direction. Reset clears DDRD[1:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Alternative Function:
Address:
Data direction register D (DDRD) does not affect the data direction of port
D pins that are being used by the TIMA. However, the DDRD bits always
determine whether reading port D returns the states of the latches or the
states of the pins. See
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Reset:
Read:
Write:
Address:
Reset:
Read:
Write:
$0007
Bit 7
0
0
Figure 12-11. Data Direction Register D (DDRD)
$0003
Bit 7
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
0
Figure 12-10. Port D Data Register (PTD)
= Unimplemented
6
0
0
= Unimplemented
6
0
Table
5
0
0
12-4.
5
0
NOTE
NOTE
4
0
0
Unaffected by reset
4
0
17.8.1 TIMA Status and Control
3
0
0
3
0
2
0
0
2
0
DDRD1
1
0
TACH1
PTD1
1
DDRD0
Bit 0
0
TACH0
PTD0
Bit 0
Register.
Port D
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