MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 178

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Serial Peripheral Interface (SPI) Module
15.6.2 Mode Fault Error
For the MODF flag (in SPSCR) to be set, the mode fault error enable bit (MODFEN in SPSCR) must be
set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again
after MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE in SPSCR)
is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF and
OVRF can generate a receiver/error CPU interrupt request. (See
only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
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2
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4
5
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READ SPSCR
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT.
CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
SPI RECEIVE
READ SPDR
COMPLETE
OVRF
ERRIE
SPRF
MODF
OVRF
Figure 15-8. Clearing SPRF When OVRF Interrupt Is Not Enabled
BYTE 1
1
Figure 15-9. SPI Interrupt Request Generation
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
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SPRIE
SPTE
3
4
SPTIE
SPRF
BYTE 2
5
SPE
BYTE 3
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8
9
8
CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
CPU READS BYTE 2 SPDR, CLEARING OVRF BIT.
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT.
CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT.
Figure
9
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
BYTE 4
15-9). It is not possible to enable
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Freescale Semiconductor
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