MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 155

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 14
System Integration Module (SIM)
14.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. The SIM is a system state controller that coordinates the central processor unit (CPU)
and exception timing. Together with the CPU, the SIM controls all microcontroller unit (MCU) activities. A
block diagram of the SIM is shown in
The SIM is responsible for:
Table 14-1
14.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in
originates from either an external oscillator or from the internal clock generator.
Freescale Semiconductor
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•
•
•
•
Bus clock generation and control for CPU and peripherals:
–
–
Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
Interrupt control:
–
–
–
CPU enable/disable timing
Modular architecture expandable to 128 interrupt sources
Stop/wait/reset entry and recovery
Internal clock control
Acknowledge timing
Arbitration control timing
Vector address generation
shows the internal signal names used in this section.
Signal Name
CGMXCLK
CGMOUT
PORRST
IRST
R/W
IDB
IAB
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Selected clock source from internal clock generator module (ICG)
Clock output from ICG module (bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset (POR) module to the SIM
Internal reset signal
Read/write signal
Table 14-1. Signal Name Conventions
Figure
14-1.
Description
Figure
14-2. This clock
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