MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 60

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Configuration Registers (CONFIG1 and CONFIG2)
LVIRSTD — LVI Reset Disable Bit
LVIPWRD — LVI Power Disable Bit
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
SSREC — Short Stop Recovery Bit
STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
60
LVIRSTD disables the reset signal from the LVI module. See
Module.
LVIPWRD disables the LVI module. See
LVI5OR3 selects the voltage operating mode of the LVI module. See
(LVI)
to operate the LVI in 3-V mode if desired. See
trip points for each of the modes.
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
If the system clock source selected is the internal oscillator or the external crystal and the
OSCENINSTOP configuration bit is not set, the oscillator will be disabled during stop mode. The short
stop recovery does not provide enough time for oscillator stabilization and thus the SSREC bit should
not be set.
When using the LVI during normal operation but disabling during stop mode, the LVI will have an
enable time of t
CGMXCLK cycles) gives a delay longer than the LVI enable time for these startup scenarios. There is
no period where the MCU is not protected from a low-power condition. However, when using the short
stop recovery configuration option, the 32-CGMXCLK delay must be greater than the LVI’s turn on time
to avoid a period in startup where the LVI is not protecting the MCU.
STOP enables the STOP instruction.
COPD disables the COP module. See
1 = LVI module resets disabled
0 = LVI module resets enabled
1 = LVI module power disabled
0 = LVI module power enabled
1 = LVI operates in 5-V mode.
0 = LVI operates in 3-V mode.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLCK cycles
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
Module. The voltage mode selected for the LVI will typically be 5 V. However, users may choose
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
Exiting stop mode by an LVI reset will result in the long stop recovery.
EN
. The system stabilization time for power-on reset and long stop recovery (both 4096
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Chapter 6 Computer Operating Properly (COP)
Chapter 11 Low-Voltage Inhibit (LVI)
Chapter 20 Electrical Specifications
NOTE
NOTE
Chapter 11 Low-Voltage Inhibit (LVI)
Chapter 11 Low-Voltage Inhibit
Module.
Freescale Semiconductor
for the LVI’s voltage
Module.