MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 214

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Timer Interface B (TIMB) Module
18.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in
Modulation
pulse width value over the value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change a pulse width value could cause
incorrect operation for up to two PWM periods. For example, writing a new value before the counter
reaches the old value but after the counter reaches the new value prevents any compare during that PWM
period. Also, using a TIMB overflow interrupt routine to write a new, smaller pulse width value may cause
the compare to be missed. The TIMB may pass the new value before it is written to the TIMB channel
registers.
Use these methods to synchronize unbuffered changes in the PWM pulse width on channel x:
18.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the
PTB6/TBCH0 pin. The TIMB channel registers of the linked pair alternately control the pulse width of the
output.
Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and
channel 1. The TIMB channel 0 registers initially control the pulse width on the PTB6/TBCH0 pin. Writing
to the TIMB channel 1 registers enables the TIMB channel 1 registers to synchronously control the pulse
width at the beginning of the next PWM period. At each subsequent overflow, the TIMB channel registers
(0 or 1) that control the pulse width are the ones written to last. TBSC0 controls and monitors the buffered
PWM function, and TIMB channel 1 status and control register (TBSC1) is unused. While the MS0B bit is
set, the channel 1 pin, PTB7/TBCH1, is available as a general-purpose I/O pin.
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When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
When changing to a longer pulse width, enable TIMB overflow interrupts and write the new value
in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at the end of the current
PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current
pulse) could cause two output compares to occur in the same PWM period.
(PWM). The pulses are unbuffered because changing the pulse width requires writing the new
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
NOTE
NOTE
Freescale Semiconductor
18.3.4 Pulse Width