MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 269

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Revision History
Changes from Rev 9.0 published in August 2005 to Rev 10 published in October 2005
Changes from Rev 8.0 published in July 2005 to Rev 9 published in August 2005
Freescale Semiconductor
Registers (CONFIG1
Computer Operating
Low-Voltage Inhibit
System Integration
Keyboard Interrupt
Timebase Module
Input/Output (I/O)
Converter (ADC)
Communications
Analog-to-Digital
Enhanced Serial
Interface (ESCI)
Properly (COP)
and CONFIG2)
Ports (PORTS)
(KBD) Module
Module (SIM)
Configuration
(LVI) Module
Throughout
Section
Section
Memory
Module
Module
Module
(TBM)
Page (in Rev 10)
Page (in Rev 9)
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
159
189
N/A
110
112
113
117
142
143
57
32
53
63
Figure 5-1. Configuration Register 2 (CONFIG2)
to ESCIBDSRC.
14.3.2.5 Forced Monitor Mode Entry Reset (MENRST)
value from $00 to $FF.
Figure 16-1. Timebase Block Diagram
TBMCLKSEL to TMBCLKSEL.
Updated to meet Freescale identity guidelines.
Changed ADRH register bit names at address location $003D from ADCH9
and ADCH8 to AD9 and AD8 respectively.
Table 3-2. ADC Clock Divide Ratio — Changed last table entry under ADC
Clock Rate from ADC input clock ÷ 6 to ADC input clock ÷ 16.
6.6 Monitor Mode — changed V
10.7.2 Keyboard Interrupt Enable Register — In bit definition changed PDx
to KBDx.
11.3.1 Polled LVI Operation — Changed LVIRSTD bit must be at 0 to enable
LVI resets to LVIRSTD bit must be at 1 to disable LVI resets
11.5.2 Stop Mode — Changed LVIPWRD bit in the configuration register
programmed to 0 to LVIPWRD bit in the configuration register programmed
to 1
Figure 12-4. Port B Data Register (PTB) — Changed ATD7–ATD0 to
AD7–AD0 in both the bit descriptions and alternative function blocks.
13.8.3 ESCI Control Register 3 — In the bit description for PEIE, changed
ESCI receiver CPU interrupt request to ESCI error CPU interrupt request
13.8.4 ESCI Status Register 1 — In the bit description for IDLE, changed
ESCI error CPU interrupt request to ESCI receiver CPU interrupt request.
Description of change
Description of change
DD
= V
— Corrected label from
TST
is present to V
— Corrected name for bit 6
— Corrected erased
TST
is present.
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