MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 235
MC68HC908GP16CFB
Manufacturer Part Number
MC68HC908GP16CFB
Description
MCU 8-BIT 16K FLASH 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908EY16VFAR2.pdf
(278 pages)
Specifications of MC68HC908GP16CFB
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Quantity
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Part Number:
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With V
and the baud rate is a nominal 6300.
When the forced monitor mode is entered the COP is always disabled regardless of the state of IRQ or
RST.
19.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
Table 19-2
19.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
19.3.1.5 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of approximately two bits and then echoes back the break signal.
19.3.1.6 Baud Rate
The communication baud rate is controlled by the crystal frequency or external clock and the state of the
PTB5 pin (when IRQ is set to V
on IRQ and the reset vector blank, then the baud rate is independent of PTB5.
Freescale Semiconductor
SS
on IRQ at the monitor entry, the ICG is on. In this case, the bus frequency is a nominal 1.6 MHz
summarizes the differences between user mode and monitor mode.
User
Monitor
Modes
START
BIT
Vector High
0
$FFFE
$FEFE
Reset
BIT 0
1
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
2
BIT 1
TST
MISSING STOP BIT
3
Vector Low
Figure 19-12. Monitor Data Format
) upon entry into monitor mode. If monitor mode was entered with V
$FFFF
$FEFF
Figure 19-13. Break Transaction
4
Reset
BIT 2
Table 19-2. Mode Differences
5
6
BIT 3
Vector High
7
$FFFC
$FEFC
Break
BIT 4
Functions
BIT 5
Vector Low
APPROXIMATELY 2 BITS DELAY
BEFORE ZERO ECHO
$FEFD
$FFFD
Break
BIT 6
0
1
BIT 7
2
Vector High
$FFFC
$FEFC
3
STOP
SWI
BIT
4
START
NEXT
5
BIT
6
Vector Low
Monitor Module (MON)
$FEFD
$FFFD
SWI
7
DD
235
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