MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 132

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Enhanced Serial Communications Interface (ESCI) Module
13.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1
(SCC1) determines character length. When receiving 9-bit data, bit R8 in ESCI control register 3 (SCC3)
is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7).
13.4.3.2 Character Reception
During an ESCI reception, the receive shift register shifts characters in from the RxD pin. The ESCI data
register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the SCDR. The ESCI receiver full bit, SCRF, in ESCI status register 1 (SCS1) becomes set, indicating
that the received byte can be read. If the ESCI receive interrupt enable bit, SCRIE, in SCC2 is also set,
the SCRF bit generates a receiver CPU interrupt request.
13.4.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at these times
(see
To locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s.
When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
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Figure
After every start bit
After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at
RT8, RT9, and RT10 returns a valid 1 and the majority of the next RT8, RT9, and RT10 samples
returns a valid 0)
13-6):
RT CLOCK
RT CLOCK
SAMPLES
CLOCK
RESET
STATE
RxD
RT
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Figure 13-6. Receiver Data Sampling
QUALIFICATION
START BIT
VERIFICATION
START BIT
START BIT
SAMPLING
DATA
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