MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 146

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Enhanced Serial Communications Interface (ESCI) Module
13.8.6 ESCI Data Register
The ESCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the ESCI data register.
R7/T7:R0/T0 — Receive/Transmit Data Bits
13.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
LINR — LIN Receiver Bit
146
Reading address $0015 accesses the read-only received data bits, R7:R0. Writing to address $0015
writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register.
This read/write bit selects the enhanced ESCI features for slave nodes in the local interconnect
network (LIN) protocol as shown in
In LIN (version 1.2) systems, the master node transmits a break character which will appear as
11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
Address:
Address:
Do not use read-modify-write instructions on the ESCI data register.
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Reset:
Reset:
Read:
Read:
Write:
Write:
$0015
$0016
Bit 7
Bit 7
R7
LINR
T7
R
R
0
0
1
1
Figure 13-16. ESCI Baud Rate Register (SCBR)
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Figure 13-15. ESCI Data Register (SCDR)
= Reserved
M
LINR
X
0
1
R6
T6
6
6
0
Table 13-6. ESCI LIN Control Bits
Normal ESCI functionality
13-bit break detect enabled for LIN receiver
14-bit break detect enabled for LIN receiver
Table
SCP1
R5
T5
5
5
0
13-6. Reset clears LINR.
NOTE
NOTE
Unaffected by Reset
SCP0
R4
T4
4
4
0
Functionality
R3
T3
R
3
3
0
SCR2
R2
T2
2
2
0
SCR1
R1
T1
1
1
0
Freescale Semiconductor
SCR0
Bit 0
Bit 0
R0
T0
0