MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 93

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

If the clock period needs more than doubled or halved, the same relationship applies, only for each time
the clock period needs doubled, the total number of cycles doubles. That is, when transitioning from fast
to slow, going from the initial speed to half speed takes 44*N*τ
takes 88*N*τ
series can be expressed as (2
doubled or halved. Since 2
44*N*(τ
Note that increasing speed takes much longer than decreasing speed since N is higher. This can be
expressed in terms of the initial clock period (τ
8.4.6.2 Settling to Within 5 Percent
Once the clock period is within 15 percent of the desired clock period, the filter starts making smaller
adjustments. When between 15 percent and 5 percent error, each correction will adjust the clock period
between 1.61 percent and 2.94 percent. In this mode, a maximum of eight corrections will be required to
get to less than 5 percent error. Since the clock period is relatively close to desired, each correction takes
approximately the same period of time, or 4*τ
be set and the clock frequency is usable, although the error will be as high as 5 percent. The total time to
this point is:
8.4.6.3 Total Settling Time
Once the clock period is within 5 percent of the desired clock period, the filter starts making minimum
adjustments. In this mode, each correction will adjust the frequency between 0.202 percent and 0.368
percent. A maximum of 24 corrections will be required to get to the minimum error. Each correction takes
approximately the same period of time, or 4*τ
this makes 32 corrections (128*τ
minimum error is:
The equations for τ
the nominal. This means the variability in the ICLK frequency due to process, temperature, and voltage
must be considered. Additionally, other process factors and noise can affect the actual tolerances of the
points at which the filter changes modes. This means a worst case adjustment of up to 35 percent (ICLK
clock period tolerance plus 10 percent) must be added. This adjustment can be reduced with trimming.
Table 8-3
Freescale Semiconductor
ICLKSLOW
shows some typical values for settling time.
ICLKFAST
1/ (307.2 kHz)
1/ (6.45 MHz)
1/ (25.8 MHz)
1/ (25.8 MHz)
–τ
15
ICLKFAST
, τ
τ
; going from quarter speed to eighth speed takes 176*N*τ
1
5
, and τ
x
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
).
happens to be equal to τ
Table 8-3. Typical Settling Time Examples
x
tot
–1)*44*N*τ
IBASE
τ
are dependent on the actual initial and final clock periods τ
tot
τ
5
1/ (307.2 kHz)
1/ (25.8 MHz)
1/ (6.45 MHz)
1/ (25.8 MHz)
=
=
) to get from 15 percent to the minimum error. The total time to the
τ
abs 44N τ
abs 44N τ
τ
15
2
ICLKFAST
=
[
[
IBASE
IBASE
abs 44N τ
1
) minus the final clock period (τ
(
(
[
. Added to the corrections for 15 percent to 5 percent,
. At this point, the internal clock stable bit (ICGS) will
1
1
, where x is the number of times the speed needs
84
21
84
N
1
–
–
ICLKSLOW
τ
τ
2
2
(
)
)
1
]
]
11.9 ms
+
+
430 µs
107 µs
141 µs
–
τ
32τ
128τ
τ
15
ICLKFAST
2
/τ
)
]
ICLKFAST
IBASE
IBASE
12.0 ms
; from half speed to quarter speed
535 µs
212 µs
246 µs
τ
, the equation reduces to
5
ICLKFAST
2
) as such:
12.3 ms
850 µs
525 µs
560 µs
τ
tot
; and so on. This
1
Usage Notes
and τ
2
, not
93