MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 96

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Internal Clock Generator (ICG) Module
8.6.4 Oscillator Enable In Stop (OSCENINSTOP)
Oscillator enable in stop (OSCENINSTOP), when set, will enable the ICG to continue to generate clocks
(either CGMXCLK, CGMOUT, or TBMCLK) in stop mode. This function is used to keep the timebase
running while the rest of the microcontroller stops. When OSCENINSTOP is clear, all clock generation
will cease and CGMXCLK, CGMOUT, and TBMCLK will be forced low during stop mode.
The default state for this option is clear.
8.7 Input/Output (I/O) Registers
The ICG contains five registers. These registers are:
Several of the bits in these registers have interaction where the state of one bit may force another bit to
a particular state or prevent another bit from being set or cleared. A summary of this interaction is shown
in
96
Reset
OSCENINSTOP = 0,
STOP = 1
EXTCLKEN = 0
CMF = 1
CMON = 0
CMON = 1
CS = 0
CS = 1
ICGON = 0
ICGON = 1
ICGS = 0
ECGON = 0
ECGS = 0
IOFF = 1
EOFF = 1
N = written
TRIM = written
—
0, 1
0*, 1*
(0), (1)
us, uc, uw
Table
1. ICG control register, ICGCR
2. ICG multiplier register, ICGMR
3. ICG trim register, ICGTR
4. ICG DCO divider control register, ICGDVR
5. ICG DCO stage control register, ICGDSR
Condition
8-4.
Register bit is forced clear or set (respectively) in the given condition.
Register bit must be clear or set (respectively) for the given condition to occur.
Register bit cannot be set, cleared, or written (respectively) in the given condition.
Register bit is unaffected by the given condition.
Register bit is temporarily forced clear or set (respectively) in the given condition.
CMIE CMF CMON CS ICGON ICGS ECQON ECQ N[6:0] TRIM[7:0] DDIV[3:0] DSTQ[7:0]
(0)
(0)
us
us
—
—
—
—
—
—
—
Table 8-4. ICG Module Register Bit Interaction Summary
0
0
0
0
0
0
(1)
(0)
(0)
—
—
—
—
—
—
1*
1*
0
0
0
0
0
0
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
(0)
(1)
(1)
(1)
(0)
(0)
us
us
—
—
—
0
0
0
1
0
0
(0)
(1)
—
—
—
—
—
uc
us
—
—
0
0
1
0
1
0
(0)
(1)
(1)
(1)
—
—
Register Bit Results for Given Condition
—
—
—
—
—
1
1
1
1
1
1
(0)
—
—
—
—
—
—
—
—
—
—
0*
0*
0
0
0
0
(0)
(1)
(1)
—
—
—
—
—
—
—
—
0
0
1
1
1
1
(0)
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
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Freescale Semiconductor
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