MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 192

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Timebase Module (TBM)
If the internal clock generator has not been enabled to operate in stop mode, the timebase module will
not be active during stop mode. In stop mode, the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce power consumption by disabling the
timebase module before executing the STOP instruction.
16.7 Timebase Control Register
The timebase has one register, the timebase control register (TBCR), which is used to enable the
timebase interrupts and set the rate.
TBIF — Timebase Interrupt Flag
TBR2–TBR0 — Timebase Divider Selection Bits
TACK— Timebase ACKnowledge Bit
TBIE — Timebase Interrupt Enabled Bit
TBON — Timebase Enabled Bit
192
This read-only flag bit is set when the timebase counter has rolled over.
These read/write bits select the tap in the counter to be used for timebase interrupts as shown in
Table
The TACK bit is a write-only bit and always reads as 0. Writing a 1 to this bit clears TBIF, the timebase
interrupt flag bit. Writing a 0 to this bit has no effect.
This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the
TBIE bit.
This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption
when its function is not necessary. The counter can be initialized by clearing and then setting this bit.
Reset clears the TBON bit.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
1 = Clear timebase interrupt flag
0 = No effect
1 = Timebase interrupt is enabled.
0 = Timebase interrupt is disabled.
1 = Timebase is enabled.
0 = Timebase is disabled and the counter initialized to 0s.
16-1.
Address: $001C
Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1).
Reset:
Read:
Write:
Bit 7
TBIF
0
Figure 16-2. Timebase Control Register (TBCR)
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Clearing TBON has no effect on the TBIF flag.
= Unimplemented
TBR2
6
0
TBR1
5
0
NOTE
NOTE
TBR0
4
0
TACK
3
R
0
0
= Reserved
TBIE
2
0
TBON
1
0
Freescale Semiconductor
Bit 0
R
0