MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 205

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MSxA — Mode Select Bit A
ELSxB and ELSxA — Edge/Level Select Bits
Freescale Semiconductor
Setting MS0B disables the channel 1 status and control register and reverts TACH1 to
general-purpose I/O.
Reset clears the MSxB bit.
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin once PWM, input
capture, or output compare operation is enabled (see
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTD0/TACH0
or pin PTD1/TACH1 is available as a general-purpose I/O pin. However, channel x is at a state
determined by these bits and becomes transparent to the respective pin when PWM, input capture, or
output compare mode is enabled.
ELSxB and ELSxA bits.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
MSxB
X
X
0
0
0
0
0
0
0
1
1
1
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIMA status and control register (TASC).
Before enabling a TIMA channel register for input capture operation, make
sure that the PTDx/TACHx pin is stable for at least two bus clocks.
MSxA
X
X
X
0
1
0
0
0
1
1
1
1
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Table 17-2. Mode, Edge, and Level Selection
ELSxA
0
0
1
0
1
0
1
0
1
1
0
1
Table
Table 17-2
Output compare
17-2.
Buffered output
buffered PWM
Output preset
Input capture
compare or
or PWM
Mode
shows how ELSxB and ELSxA work. Reset clears the
NOTE
NOTE
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
Table
17-2). Reset clears the MSxA bit.
Configuration
I/O Registers
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