MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 59

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

EXTSLOW — Slow External Crystal Enable Bit
EXTCLKEN — External Clock Enable Bit
TMBCLKSEL — Timebase Clock Select Bit
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
SSBPUENB — SS Pullup Enable Bit
COPRS — COP Rate Select Bit
LVISTOP — LVI Enable in Stop Mode Bit
Freescale Semiconductor
The EXTSLOW bit has two functions. It configures the ICG module for a fast (1 MHz to 8 MHz) or slow
(30 kHz to 100 kHz) speed crystal. The option also configures the clock monitor operation in the ICG
module to expect an external frequency higher (307.2 kHz to 32 MHz) or lower (60 Hz to 307.2 kHz)
than the base frequency of the internal oscillator. See
Module.
EXTCLKEN enables an external clock source or crystal/ceramic resonator to be used as a clock input.
Setting this bit enables PTC4/OSC1 pin to be a clock input pin. Clearing this bit (default setting) allows
the PTC4/OSC1 and PTC3/OSC2 pins to function as general-purpose input/output (I/O) pins. Refer to
Table 5-1
(ICG) Module
TMBCLKSEL enables an enable the extra divide by 128 prescaler in the timebase module. Setting this
bit enables the extra prescaler and clearing this bit disables it. Refer to
selection details.
OSCENINSTOP, when set, will enable the internal clock generator module to continue to generate
clocks (either internal, ICLK, or external, ECLK) in stop mode. See
(ICG)
stops. When clear, all clock generation will cease and both ICLK and ECLK will be forced low during
stop mode. The default state for this option is clear, disabling the ICG in stop mode.
Clearing SSBPUENB enables the SS pullup resistor.
COPRS selects the COP timeout period. Reset clears COPRS. See
Properly (COP)
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = ICG set for slow external crystal operation
0 = ICG set for fast external crystal operation
1 = Allows PTC4/OSC1 to be an external clock connection
0 = PTC4/OSC1 and PTC3/OSC2 function as I/O port pins (default).
1 = Enables extra divide by 128 prescaler in timebase module.
0 = Disables extra divide by 128 prescaler in timebase module.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
1 = Disables SS pullup resistor.
0 = Enables SS pullup resistor.
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
Module. This function is used to keep the timebase running while the rest of the microcontroller
for configuration options for the external source. See
This bit has the same functionality as the OSCSTOPENB CONFIG bit in
MC68HC908GP20 and MC68HC908GR8 parts.
for a more detailed description of the external clock operation.
Module.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
NOTE
Chapter 8 Internal Clock Generator (ICG)
Chapter 8 Internal Clock Generator
Chapter 8 Internal Clock Generator
Chapter 6 Computer Operating
Table 16-1
Functional Description
for timebase divider
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