MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 87

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.3.5 Clock Selection Circuit
The clock selection circuit, shown in
output clock (CGMXCLK) and the timebase clock (TBMCLK) from either the internal clock (ICLK) or the
external clock (ECLK). The clock selection circuit also contains a divide-by-two circuit which creates the
clock generator output clock (CGMOUT), which generates the bus clocks.
8.3.5.1 Clock Selection Switches
The first switch creates the oscillator output clock (CGMXCLK) from either the internal clock (ICLK) or the
external clock (ECLK), based on the clock select bit (CS; set selects ECLK, clear selects ICLK). When
switching the CS bit, both ICLK and ECLK must be on (ICGON and ECGON set). The clock being
switched to also must be stable (ICGS or ECGS set).
The second switch creates the timebase clock (TBMCLK) from ICLK or ECLK based on the external clock
on bit. When ECGON is set, the switch automatically selects the external clock, regardless of the state of
the ECGS bit.
8.3.5.2 Clock Switching Circuit
To robustly switch between the internal clock (ICLK) and the external clock (ECLK), the switch assumes
the clocks are completely asynchronous, so a synchronizing circuit is required to make the transition.
When the select input (the clock select bit for the oscillator output clock switch or the external clock on bit
for the timebase clock switch) is changed, the switch will continue to operate off the original clock for
between one and two cycles as the select input is transitioned through one side of the synchronizer. Next,
the output will be held low for between one and two cycles of the new clock as the select input transitions
through the other side. Then the output starts switching at the new clock’s frequency. This transition
guarantees that no glitches will be seen on the output even though the select input may change
Freescale Semiconductor
RESET
ECGON
EOFF
ECLK
ICLK
IOFF
V
CS
NAME
NAME
SS
Figure 8-8. Clock Selection Circuit Block Diagram
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
CONFIGURATION REGISTER BIT
TOP LEVEL SIGNAL
Figure
8-8, contains two clock switches which generate the oscillator
SELECT
ICLK
ECLK
IOFF
EOFF
FORCE_I
FORCE_E
SELECT
ICLK
ECLK
IOFF
EOFF
FORCE_I
FORCE_E
SYNCHRONIZING
SYNCHRONIZING
SWITCHER
SWITCHER
CLOCK
CLOCK
OUTPUT
OUTPUT
NAME
NAME
DIV2
REGISTER BIT
MODULE SIGNAL
CGMXCLK
CGMOUT
TBMCLK
Functional Description
87