MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet - Page 211

• Manufacturer Part Number: MC68HC908GP16CFB
• Description: MCU 8-BIT 16K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

18.3.1 TIMB Counter Prescaler
The TIMB clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMB status and control register
select the TIMB clock source.
18.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TBSC0 through TBSC1
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIMB latches the contents of the TIMB counter into the TIMB channel
registers, TBCHxH–TBCHxL. Input captures can generate TIMB CPU interrupt requests. Software can
determine that an input capture event has occurred by enabling input capture interrupts or by polling the
status flag bit.
The free-running counter contents are transferred to the TIMB channel status and control register
(TBCHxH–TBCHxL, see
whether the TIMB channel flag (CH0F–CH1F in TBSC0–TBSC1 registers) is set or clear. When the status
flag is set, a CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time
of the event. Because this value is stored in the input capture register 2 bus cycles after the actual event
Freescale Semiconductor
BUS CLOCK
INTERNAL
TSTOP
TRST
16-BIT COMPARATOR
16-BIT COMPARATOR
16-BIT COMPARATOR
TBMODH:TBMODL
16-BIT COUNTER
TBCH0H:TBCH0L
TBCH1H:TBCH1L
16-BIT LATCH
16-BIT LATCH
CHANNEL 0
CHANNEL 1
PRESCALER
18.8.5 TIMB Channel
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Figure 18-2. TIMB Block Diagram
ELS0B
ELS1B
MS0A
MS1A
PS2
PRESCALER SELECT
ELS0A
ELS1A
PS1
Registers) on each proper signal transition regardless of
CH0F
MS0B
CH1F
PS0
CH0MAX
CH1MAX
CH0IE
CH1IE
TOV0
TOV1
TOIE
TOF
INTERRUPT
INTERRUPT
INTERRUPT
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
PTB6
PTB7
Functional Description
PTB7/TBCH1
PTB6/TBCH0
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