XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 164

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 4: Block RAM
Table 4-23: Block RAM (RAMB36SDP) Attributes
Table 4-24: FIFO (FIFO36_72) Attributes
164
EN_ECC_WRITE
EN_ECC_READ
DO_REG
EN_SYN
ALMOST_EMPTY_OFFSET
ALMOST_FULL_OFFSET
FIRST_WORD_FALL_THROUGH
EN_ECC_WRITE
EN_ECC_READ
DO_REG
Attribute Name
Attribute Name
Block RAM and FIFO ECC Attributes
1-bit Binary
In addition to the built-in registers in the decode and correct logic, the RAMB36SDP
primitive allows the use of optional pipeline registers controlled by the DO_REG attribute
to produce higher performance with one additional latency.
the block RAM and FIFO ECC attributes.
Boolean
Boolean
Type
Boolean TRUE, FALSE
Boolean TRUE, FALSE
Boolean TRUE, FALSE
Boolean TRUE, FALSE
Binary
Type
1-bit
9-bit
9-bit
Hex
Hex
TRUE, FALSE
TRUE, FALSE
Values
See
See
0, 1
Values
Table 4-19
Table 4-19
0, 1
www.xilinx.com
See
See
Default
FALSE
FALSE
Default
FALSE
FALSE
FALSE
FALSE
Table 4-19
Table 4-19
0
1
enable ECC functionality in a
FIFO36_72.
Enables register mode or latch mode. See
Table 4-17
synchronous FIFOs.
When set to TRUE, ties WRCLK and
RDCLK together.
When set to TRUE, FWFT must be
FALSE.
When set to FALSE, DO_REG must be 1.
Setting determines the difference
between EMPTY and ALMOST_EMPTY
conditions. Must be set using
hexadecimal notation.
Setting determines the difference
between FULL and ALMOST_FULL
conditions. Must be set using
hexadecimal notation.
When set to TRUE, the first word written
into the empty FIFO36_72 appears at the
FIFO36_72 output without RDEN
asserted.
Both attributes must be set to TRUE to
Set to TRUE to enable ECC encoder.
Set to TRUE to enable ECC decoder.
Enables register mode or latch mode.
Table 4-23
for details on multirate and
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Notes
Notes
and
Table 4-24
list