XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 181

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table 5-5
configuration.
Table 5-5: Distributed RAM Configuration
For single-port configurations, distributed RAM has a common address port for
synchronous writes and asynchronous reads. For dual-port configurations, distributed
RAM has one port for synchronous writes and asynchronous reads, and another port for
asynchronous reads. In simple dual-port configuration, there is no data out (read port)
from the write port. For quad-port configurations, distributed RAM has one port for
synchronous writes and asynchronous reads, and three additional ports for asynchronous
reads.
In single-port mode, read and write addresses share the same address bus. In dual-port
mode, one function generator is connected with the shared read and write port address.
The second function generator has the A inputs connected to a second read-only port
address and the WA inputs shared with the first read/write port address.
Figure 5-6
occupying one SLICEM. When using x2 configuration (RAM32X2Q), A6 and WA6 are
driven High by the software to keep O5 and O6 independent.
Notes:
1. S = single-port configuration; D = dual-port configuration; Q = quad-port configuration; SDP = simple
2. RAM32M is the associated primitive for this configuration.
3. RAM64M is the associated primitive for this configuration.
dual-port configuration.
shows the number of LUTs (four per slice) occupied by each distributed RAM
through
32 x 6SDP
64 x 3SDP
32 x 2Q
64 x 1Q
128 x 1D
128 x 1S
256 x 1S
32 x 1D
64 x 1D
32 x 1S
64 x 1S
Figure 5-14
RAM
(2)
(3)
www.xilinx.com
(2)
(3)
illustrate various example distributed RAM configurations
Number of LUTs
1
2
4
4
1
2
4
4
2
4
4
CLB Overview
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