XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 38

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 1: Clock Resources
X-Ref Target - Figure 1-17
38
All clock regions are 20 CLBs tall (10 CLBs above
span half the die
All clock regions
and 10 CLBs below a horizontal clock line)
XC5VLX30 has 8 Clock Regions
Clock Tree and Nets - GCLK
Clock Regions
Virtex-5 clock trees are designed for low-skew and low-power operation. Any unused
branch is disconnected. The clock trees also manage the load/fanout when all the logic
resources are used.
All global clock lines and buffers are implemented differentially. This facilitates much
better duty cycles and common-mode noise rejection.
In the Virtex-5 architecture, the pin access of the global clock lines are not limited to the
logic resources clock pins. The global clock lines can access other pins in the CLBs without
using local interconnects. Applications requiring a very fast signal connection and large
load/fanout benefit from this architecture.
Virtex-5 devices improve the clocking distribution by the use of clock regions. Each clock
region can have up to 10 global clock domains. These 10 global clocks can be driven by any
combination of the 32 global clock buffers. The dimensions of a clock region are fixed to
20 CLBs tall (40 IOBs) and spanning half of the die
of the clock region, larger Virtex-5 devices can have more clock regions. As a result,
Virtex-5 devices can support many more multiple clock domains than previous FPGA
architectures.
logic resources in the center column (CMTs, IOBs, etc.) are located in the left clock regions.
The CMTs, if used, utilize the global clocks in the left regions as feedback lines. Up to four
CMTs can be in a specific region. If used in the same region, IDELAYCTRL uses another
global clock in that region. See
10 CLBs
10 CLBs
Table 1-5
Figure 1-17: Clock Regions
shows the number of clock regions in each Virtex-5 device. The
www.xilinx.com
Chapter 2, Clock Management
Center Column
Logic Resources
XC5VLX330 has 24 Clock Regions
(Figure
1-17). By fixing the dimensions
Technology.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_1_17_042406