XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 337

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IDELAYCTRL Overview
The timing diagram in
I/O switches from input to an output using 3-state control. The switching characteristics
shown in the diagram are specified in the Virtex-5 FPGA Data Sheet.
X-Ref Target - Figure 7-14
3-state control activities on the OBUF of the IOB and ODDR flip-flop to PAD timing are in
parallel with each other, depending on the ODELAY_VALUE setting the final output value
in response to a clock edge at the ODDR CLK pin is valid before or after the pad is driven
from the 3-state control. After the 3-state control propagates through to the PAD and the
IODELAY is turned around, the clock-to-output time of the ODDR flip-flop through the
IODELAY element (with the ODELAY_VALUE setting) solely determines the clock-to-
output time to the pad.
If the IODELAY or ISERDES primitive is instantiated with the IOBDELAY_TYPE attribute
set to FIXED or VARIABLE, the IDELAYCTRL module must be instantiated. The
IDELAYCTRL module continuously calibrates the individual delay elements (IODELAY)
in its region (see
temperature variations. The IDELAYCTRL module calibrates IODELAY using the user
supplied REFCLK.
Figure 7-14: Relevant Timing Signals used to Examine IODELAY Timing when an
TSCONTROL
ODDR CLK
DATAOUT
PAD
Figure 7-17, page
Previous PAD
Figure 7-14
IOB Changes from an Input to an Output
input value
ODELAY_VALUE = 0
www.xilinx.com
T
Clock-to-Out with
OCKQ
ODELAY_VALUE = 63
T
OCKQ
Clock-to-Out with
+ T
T
Clock to PAD being driven or
OCKQ
IODDO_ODATAIN
shows the relevant signal timing for the case where the
340), to reduce the effects of process, voltage, and
+ T
IODDO_ODATAIN
T
IOTP
Input/Output Delay Element (IODELAY)
+ T
IOOP
Clock to DATAOUT is variable
based on internal timing the
ODELAY_VALUE (0-63)
IODELAY_05_082107
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