XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 81

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-1FFG1136C

Manufacturer Part Number
XC5VLX50T-1FFG1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

Total Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
7200
No. Of Gates
50000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
480
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1564

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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DCM with PLL
The PLL can be used to drive the DCM to reduce the source clock’s incoming jitter before
inputting DCM. This setup reduces the source clock jitter while enabling user access to all
available DCM clock outputs.
same CMT block using the dedicated routing resource (without BUFG).
X-Ref Target - Figure 2-14
IBUFG
www.xilinx.com
Figure 2-14: PLL Driving DCM
Figure 2-14
CLKIN1
CLKFBIN
RST
CLKIN
CLKFBIN
RST
illustrates the PLL driving a DCM within the
DCM
PLL
CLKFBOUT
CLKFX180
CLK2X180
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLK180
CLK270
CLKDV
CLK2X
CLKFX
CLK90
CLK0
BUFG
BUFG
ug190_2_15_040906
Application Examples
81

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