MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 100

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

READ:
WRITE:
RESET:
TIE — Transmit Interrupt Enable
TCIE — Transmit Complete Interrupt Enable
RIE — Receiver Interrupt Enable
ILIE — Idle Line Interrupt Enable
TE — Transmitter Enable
RE — Receiver Enable
RWU — Receiver Wake-up
SBK — Send Break
MOTOROLA
7-10
Any time
Any time
$00
0 – TDRE interrupts disabled
1 – SCI interrupt if TDRE = 1
0 – TC interrupts disabled
1 – SCI interrupt if TC = 1
0 – RDRF and OR interrupts disabled
1 – SCI interrupt if RDRF or OR = 1
0 – IDLE interrupts disabled.
1 – SCI interrupt if IDLE = 1
When the transmit enable bit is set, the transmit shift register output is applied to the TXD
line. Depending on the state of control bit M (SCCR1), a preamble of 10 (M = 0) or 11 (M
= 1) consecutive ones is transmitted when software sets the TE bit from a cleared state.
After loading the last byte in the serial communications data register and receiving the
TDRE flag, the user can clear TE. Transmission of the last byte will then be completed
before the transmitter gives up control of the TXD pin. While the transmitter is active, the
data direction register control for Port D bit 1 is overridden and the line is forced to be an
output.
When the receiver enable bit is set, the receiver is enabled. When RE is clear, the receiver
is disabled and all of the status bits associated with the receiver (RDRF, IDLE, OR, NF
and FE) are inhibited. While the receiver is enabled, the data direction register control
for Port D bit 0 is overridden and the line is forced to be an input.
When the receiver wake-up bit is set by the user software, it puts the receiver to sleep
and enables the wake-up function. If the WAKE bit is cleared, RWU is cleared by the SCI
logic after receiving 10 (M = 0) or 11 (M = 1) consecutive ones. If the WAKE bit is set, RWU
is cleared by the SCI logic after receiving a data word whose MSB is set.
If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M
= 1) zeros and then reverts to idle sending data. If SBK remains set, the transmitter will
continually send whole blocks of zeros (sets of 10 or 11) until cleared. At the completion
SERIAL COMMUNICATIONS INTERFACE
MC68HC11G5