MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 107

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

As shown in Figure 8-1, four different timing relationships may be selected by control bits CPOL and
CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the MOSI line a half cycle before
the clock edge (SCK), in order for the slave device to latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a slave device,
SPR0 and SPR1 have no effect on the operation of the SPI.
8.2.4
Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It must be in the active low state
prior to data transactions and must stay low for the duration of the transaction.
The SS line on the master must be tied high. If it goes low, a mode fault error flag (MODF) is set in
the serial peripheral status register (SPSR). The SS pin can be selected to be a general-purpose
output by writing a one in bit 5 of the Port D data direction register, thus disabling the mode fault
circuit. The other three SPI lines are dedicated to the SPI whenever the SPI is on.
When CPHA = 0, the shift clock is the logical OR of SS and SCK. In this clock phase mode, SS must
go high between successive characters in an SPI message. When CPHA = 1, SS may be left low
for several SPI characters. If there is only one SPI slave MCU, its SS line may be tied to V
provided
SS
CPHA = 1 clock modes are used.
Figure 8-2 shows a block diagram of the serial peripheral interface circuitry. When a master device
transmits data to a slave device via the MOSI line, the slave device responds by sending data to the
master device via the master’s MISO line. This implies full duplex transmission with both data out
and data in synchronized to the same clock signal. Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate transmitter-empty and receiver-full status bits. A
single status bit (SPIF) is used to signify that the I/O operation has been completed.
The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the
transfer is not interrupted, and the write will be unsuccessful. This condition will cause the write
collision status bit (WCOL) in the SPSR to be set. After a data byte is shifted, the SPIF flag in the
SPSR is set.
In master mode, the SCK pin is an output. It idles high or low, depending on the SPOL bit in the
SPCR, until data is written to the shift register, at which point eight clocks are generated to shift the
eight bits of data, after which SCK goes idle again.
In slave mode, the slave start logic receives a logic low on the SS pin and a clock input at the SCK
pin. Thus, the slave is synchronized to the master. Data from the master is received serially via the
slave MOSI line and is loaded into the 8-bit shift register. The data is then transferred, in parallel,
from the 8-bit shift register to the read buffer. During a write cycle, data is written into the shift register,
then the slave waits for a clock train from the master to shift the data out on the slave’s MISO line.
Figure 8-3 illustrates the MOSI, MISO and SS master-slave interconnections.
MC68HC11G5
SERIAL PERIPHERAL INTERFACE
MOTOROLA
8-3