MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 130

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

10.5.7 Enable Register (PWEN)
Each timer has an enable bit (PWENx) to start its waveform output. Writing any of these PWENx
bits to one causes the associated Port H line to become an output regardless of the state of the
associated DDR bit. This does not change the state of the DDR bit and, when PWENx returns to
zero, the DDR bit again controls the I/O state. On the front end of the PWM timer the clock is enabled
to the PWM circuit by the PWENx enable bit being high. A synchronizing circuit guarantees that the
clock will only be enabled or disabled at an edge.
READ:
WRITE:
RESET:
PWEN4 — Pulse Width Channel 4 Enable
PWEN3 — Pulse Width Channel 3 Enable
PWEN2 — Pulse Width Channel 2 Enable
PWEN1 — Pulse Width Channel 1 Enable
MOTOROLA
10-10
RESET:
Any time.
Any time.
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1 – PWM channel 4 is enabled. The pulse modulated signal becomes available at
0 – PWM channel 4 is disabled.
1 – PWM channel 3 is enabled. The pulse modulated signal becomes available at
0 – PWM channel 3 is disabled.
1 – PWM channel 2 is enabled. The pulse modulated signal becomes available at
0 – PWM channel 2 is disabled.
1 – PWM channel 1 is enabled. The pulse modulated signal becomes available at
0 – PWM channel 1 is disabled.
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Port H bit 3 when its clock source begins its next cycle.
Port H bit 2 when its clock source begins its next cycle.
Port H bit 1 when its clock source begins its next cycle.
Port H bit 0 when its clock source begins its next cycle.
0
7
0
6
0
0
PULSE WIDTH MODULATION TIMER
5
0
0
4
0
0
PWEN4 PWEN3 PWEN2 PWEN1
3
0
2
0
1
0
0
0
PWEN
MC68HC11G5