MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 153

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

Negative (N) — The negative bit is set if the result of the last arithmetic, logic or data manipulation
operation was negative; otherwise, the N bit is cleared. A result is said to be negative if its most
significant bit is set to one.
I Interrupt Mask (I) — The I interrupt mask bit is set, either by hardware or software, to disable (mask)
all maskable interrupt sources (both external and internal).
Half Carry (H) — The half carry bit is set when a carry occurs between bits 3 and 4 of the ALU during
an ADD, ABA or ADC instruction; otherwise, the H bit is cleared.
X Interrupt Mask (X) — The X interrupt mask bit is set only by hardware (RESET or XIRQ
acknowledge) and is cleared only by a software instruction (TAP or RTI).
Stop Disable (S) — The stop disable bit is set to disable the STOP instruction, and cleared to enable
the STOP instruction. The S bit is program controlled. The STOP instruction is treated as no
operation (NOP) if the S bit is set.
12.2
ADDRESSING MODES
In the M68HC11 CPU, six addressing modes can be used to reference memory; immediate, direct,
extended, indexed (with either of two 16-bit index registers and an 8-bit offset), inherent, and
relative. Some instructions require an additional byte before the opcode to accommodate a multi-
page opcode map; this byte is called a pre-byte.
The following paragraphs provide a description of each addressing mode. In these descriptions the
term “effective address” is used to indicate the memory address from which the argument is fetched
or stored, or from which execution is to proceed.
12.2.1 Immediate Addressing (IMM)
In the immediate addressing mode, the actual argument is contained in the byte(s) immediately
following the instruction, where the number of bytes matches the size of the register. These are two,
three, or four (if pre-byte is required) byte instructions.
12.2.2 Direct Addressing (DIR)
In the direct addressing mode (sometimes called page zero addressing), the least significant byte
of the operand address is contained in a single byte following the opcode. The high order byte of
the effective address is assumed to be $00 and is not included as an instruction byte. Direct
addressing allows the user to access $0000 through $00FF using 2-byte instructions and execution
time is reduced by eliminating the additional memory access. In most applications, this 256-byte
area is reserved for frequently referenced data. In the MC68HC11G5, software can configure
the memory map so that internal RAM, and/or internal registers or external memory can occupy
these addresses.
MC68HC11G5
CPU, ADDRESSING MODES AND INSTRUCTION SET
MOTOROLA
12-3