MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 109

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC11G5
Due to data direction register control of SPI outputs and the Port D wire-OR mode (DWOM) option,
the SPI system can be configured in a variety of ways. Systems with a single bidirectional data path
rather than separate MISO and MOSI paths can be accommodated. Since MC68HC11G5 slaves
can selectively disable their MISO output, a broadcast message protocol is also possible.
There are three registers in the serial peripheral interface which provide control, status and data
storage functions. These registers are called the serial peripheral control register (SPCR), the serial
peripheral status register (SPSR) and the serial peripheral data I/O register (SPDAT).
8.4.1
READ:
WRITE:
SPIE — SPI Interrupt Enable
SPE — SPI System Enable
8.4
SPI REGISTERS
Control Register (SPCR)
SPI Clock Generator
RESET:
Any time
Any time.
0 – SPI interrupts disabled.
1 – SPI interrupts enabled.
When this bit is set to one, a hardware interrupt sequence is requested each time the
SPIF or MODF status flag is set. SPI interrupts are inhibited if this bit is clear or if the I
bit in the CC Register is set.
0 – SPI system off.
1 – SPI system on.
$1028
Figure 8-3. Serial Peripheral Interface Master-Slave Interconnection
SPIE
7
0
8-bit Shift Register
SPE
6
0
Master
SERIAL PERIPHERAL INTERFACE
DWOM
5
0
MSTR
4
0
MISO
MOSI
SCK
SS
CPOL
3
0
+5V
MISO
MOSI
SCK
SS
CPHA
2
1
SPR1
U
1
8-bit Shift Register
SPR0
Slave
U
0
SPCR
MOTOROLA
8-5