MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 69

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC11G5
The MC68HC11G5 has a WAIT mode to suspend processing and reduce power consumption to an
intermediate level. The MC68HC11G5 also offers a STOP mode which turns off all on-chip
clocks and reduces power consumption to an absolute minimum while retaining the contents of all
512 bytes of RAM.
5.3.1
WAIT mode is invoked by executing the WAI opcode. The CPU registers are stacked and
CPU processing is suspended until a qualified interrupt is detected. The interrupt can be an external
IRQ, an XIRQ, or any of the internally generated interrupts such as the timer or serial interrupts.
The on-chip crystal oscillator remains active throughout the WAIT standby period.
The reduction of power in WAIT mode depends on how many internal clock signals driving on-chip
peripheral functions can be shut down. The CPU is always shut down in WAIT mode. The free-
running timer system is shut down in WAIT mode if, and only if, the I bit is set to one and the
COP system is disabled by NOCOP being set to one. Several other systems may also be in a
reduced power consumption state depending upon the state of software controlled configuration
control bits. Power consumption by the A/D is not significantly affected by WAIT mode. However,
the A/D current can be eliminated by writing the ADPU bit to zero. The SPI system is enabled or
disabled by the SPE control bit. The SCI transmitter is enabled or disabled by the TE bit, and the
SCI receiver is enabled or disabled by the RE bit.
The power consumption in WAIT mode is very dependent, therefore, on the particular application.
5.3.2
STOP mode is invoked by executing the STOP instruction while the S bit in the CCR is equal to zero.
If the S bit is not zero then the STOP opcode is treated as a no-op (NOP). STOP mode offers
minimum power consumption because all clocks including the crystal oscillator are stopped while
in this mode. To exit the STOP mode and resume normal processing, a logic low level must be
applied to one of the external interrupts (IRQ or XIRQ) or to the RESET pin. A pending edge-
triggered IRQ can also bring the CPU out of STOP mode.
Since all clocks are stopped in this mode, all internal peripheral functions also stop. The data in the
internal RAM is retained as long as VDD power is maintained. The CPU state and I/O pin levels are
static and are unchanged by the STOP mode. Therefore, when an interrupt comes to restart the
system, the MC68HC11G5 resumes processing as if there were no interruption. If reset is used to
restart the system a normal reset sequence results where all I/O pins and functions are also restored
to their initial states.
In order for the IRQ pin to be used as a means of recovering from the STOP mode, the I bit in the
CCR must be clear (IRQ not masked). The XIRQ input may be used to wake up the MCU from STOP
regardless of the state of the X bit in the CCR, although the recovery sequence depends on the state
of the X bit. If X is set to zero (XIRQ not masked), the MCU will start up beginning with the stacking
5.3
LOW POWER MODES
WAIT
STOP
RESETS, INTERRUPTS AND LOW POWER MODES
MOTOROLA
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