MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 74

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

and I6/O7 bits in the TCTL4 register. Output compare actions are controlled by bits in TCTL1, TCTL3
and CFORC. Input capture control is via registers TCTL2 and TCTL3. Registers TMSK1 and TMSK2
provide interrupt enable bits for input capture and output compare functions. TFLG1 and TFLG2
provide corresponding interrupt flag bits.
The real time interrupt feature on the MC68HC11G5 is configured and controlled using three bits
(RTR2, RTR1 and RTR0) in the PACTL register to select one of eight interrupt rates. The RTII bit
in the TMSK2 register enables the interrupt capability. Every timeout causes the RTIF bit in TFLG2
to be set, and if RTII is set, an interrupt request is generated. After reset, one entire real time interrupt
period elapses before the RTIF flag is set for the first time.
The pulse accumulator is an 8-bit read/write counter (PACNT) which can operate in either of two
modes (external event counting or gated time accumulation) depending on the state of the PAMOD
control bit in the PACTL register. In the event counting mode, the 8-bit counter is clocked to
increasing values by an external pin input. The maximum clocking rate for the external event
counting mode is E divided by 2. In the gated time accumulation mode a free-running E/64 clock
drives the 8-bit counter, but only while the external PAI input pin is in a selected state.
Although Port A bit 7 would normally be configured as an input when being used for the pulse
accumulator, it still drives the pulse accumulator system even when it is configured for use in its other
functions. DDRA bit 7 controls the data direction of Port A bit 7. When DDRA bit 7 is zero, Port A
bit 7 is an input only pin, unless OC1 is configured to control the pin. When DDRA bit 7 is a one, Port
A bit 7 is an output but is still connected to the pulse accumulator input.
PAEN in the PACTL register enables/disables the pulse accumulator.
PEDGE in the PACTL register selects the active edge of the input signal on the PAI pin.
The PAOVF status bit in the TFLG2 register is set when the counter overflows from $FF to $00.
The PAOVI mask bit in the TMSK2 register controls whether or not a hardware interrupt will be
generated when the PAOVF flag bit is set.
The PAIF flag bit in the TFLG2 register is set when an active edge is detected on the PAI input pin.
The PAII mask bit in the TMSK2 register controls whether or not a hardware interrupt will be
generated when the PAIF status bit is set.
MOTOROLA
6-4
6.2
6.3
REAL TIME INTERRUPT
PULSE ACCUMULATOR
PROGRAMMABLE TIMER
MC68HC11G5