MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 128

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

10.5.5 Polarity Select Register (PWPOL)
Each channel has a polarity bit (PPOLx) to start the cycle with a high signal or with a low signal. This
is shown on the block diagram as a multiplex select of either the Q output or the Q output of the PWM
output flip-flop. When one of the bits in the PWPOL register is set, the associated PWM channel
output is high at the beginning of the clock cycle, then goes low when the duty count is reached.
READ:
WRITE:
RESET:
PCLK4 — Pulse Width Channel 4 Clock Select
PCLK3 — Pulse Width Channel 3 Clock Select
PCLK2 — Pulse Width Channel 2 Clock Select
PCLK1 — Pulse Width Channel 1 Clock Select
Note:
PPOL4 — Pulse Width Channel 4 Polarity
MOTOROLA
10-8
RESET:
Any time.
Any time.
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1 – The clock source for PWM channel 4 is Clock S. (Clock S equals Clock A divided
0 – Clock B is the clock source for PWM channel 4.
1 – The clock source for PWM channel 3 is Clock S.
0 – Clock B is the clock source for PWM channel 3.
1 – The clock source for PWM channel 2 is Clock S.
0 – Clock A is the clock source for PWM channel 2.
1 – The clock source for PWM channel 1 is Clock S.
0 – Clock A is the clock source for PWM channel 1.
While register bits PCLK1 – 4 may be written at any time, if a clock select is changed while
a PWM signal is being generated, a truncated pulse may occur during the transition.
1 – PWM channel 4 output is high at the beginning of the clock cycle, then goes low
0 – PWM channel 4 output is low at the beginning of the clock cycle, then goes high
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by two times the value (plus one) in the PWSCAL register.)
when the duty count is reached.
when the duty count is reached.
PCLK4
7
0
PCLK3
6
0
PULSE WIDTH MODULATION TIMER
PCLK2
5
0
PCLK1
4
0
PPOL4
3
0
PPOL3
2
0
PPOL2
1
0
PPOL1
0
0
PWPOL
MC68HC11G5