MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 120

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Resets and Interrupts
Technical Data
120
MDA — Mode Select A Bit
IRVNE — Internal Read Visibility/Not E Bit
PSEL[3:0] — Priority Select Bits
The mode select A bit reflects the status of the MODA input pin at the
rising edge of reset. Refer to
On-Chip Memory
The IRVNE control bit allows internal read accesses to be available
on the external data bus during operation in expanded modes. In
single-chip and bootstrap modes, IRVNE determines whether the E
clock is driven out an external pin. For the MC68HC811E2, this bit is
IRV and only controls internal read visibility. Refer to
Operating Modes and On-Chip Memory
These bits select one interrupt source to be elevated above all other
I-bit-related sources and can be written only while the I bit in the CCR
is set (interrupts disabled).
Table 5-3. Highest Priority Interrupt Selection
PSEL[3:0]
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Resets and Interrupts
for more information.
Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI serial transfer complete
SCI serial system
Reserved (default to IRQ)
IRQ (external pin or parallel I/O)
Real-time interrupt
Timer input capture 1
Timer input capture 2
Timer input capture 3
Timer output compare 1
Timer output compare 2
Timer output compare 3
Timer output compare 4
Timer input capture 4/output compare 5
Section 4. Operating Modes and
Interrupt Source Promoted
for more information.
M68HC11E Family — Rev. 3.2
Section 4.
MOTOROLA